SANITY CHECKS ON PD INPUTS

Sanity Checks
SANITY CHECKS

We check mainly the following input files:
1. Netlist
2. SDC files
3. Library files
4. Design information

The following commands are used for performing sanity checks and generation of the reports:
check_design
check_timing
check_library
check_legality
report_constraints
report_timing
report_qor

check_design : checks the compatibility of the design and checks the potential problems like unloaded input ports and undriven output ports, mismatched pin count etc..,

check_timing : checks for any unconstrained paths as PnR tool optimizes the constrained paths

check_library : performs the consistency checks within logical and physical libraries. it checks library qualities in 

physical library quality logic
(vs)
physical library consistency logic
(vs)
logical library consistency

check_legality : checks the legalization of the cells (i.e., the cells should not be overlapped and should be placed in cut rows correctly)

report_constraints : checks and reports Worst Negative Slack(WNS), Total Negative Slack(TNS) and Design Rule Constraints(DRC) violations.

report_timing : reports timing information of the design like worst setup path

report_qor : reports qor info.(i.e., timing path group and cell count details), statistics of the current design(i.e., combo., non-combo., and total area) and also reports static power, design rule violations and compile time details.