POWER PLANNING

Power Planning
POWER PLANNING

Power planning is to be done as a part of floorplanning. It is done in order to provide the power to macros and standard cells within the I-R limit.
In any IC, power planning is done in higher metal layers bcoz, they have very less I-R drop. It is because the higher metals are less resistive.
Since the width of those metal layers is more, its resistance is less.
It can be explained by:

R = (ρ*length)/Area

Eg: For a chip having 9 metal layers, layers 8 and 9 are used in power planning.
This concept includes power pads, core rings, straps, rails.
Power pad: It is used to provide power supply from source to the entire chip i.e., to core rings. It is defined with respect to the full chip owner.
Power rings: Carries power around the core/IC/chip.
(*But now a days, bumps are used instead of rings)
Straps: Carries Vdd & Vss across the chip from rings.
(*Straps is nothing but a combination of Vdd & Vss)
Rails: Carries Vdd & Vss to blocks through horizontal metal.

Power planning issues:
1. I-R drop
2. Ground bounce
3. EM violations

1. I-R drop:

It is defined as the drop in voltage occurs due to the resistance of metal.
It is of two types:
a. Static I-R drop: The voltage drop due to the wire resistance irrespective of the cell switching is called as static I-R drop.
b. Dynamic I-R drop: It is occured while switching of the cells
 
IR Drop
IR Drop
Voltage transfer in metal a drop occurs due to resistance of metal this is known as IR drop.
 IR drops are two types
 
1. Static IR drop
    Independent of the cell switching the drop is calculated with the help of wire resistance. Methods to Improve static IR drop
     1. Increase the width of wire
     2. Provide more number of wire
                
 2 . Dynamic Power Drop
      Dynamic IR drop:ir drop is calculated with the help of the switching of the cells. We can improve dynamic IR drop by below methods:      
      1. Placing dcap cells in between them
      2. Increase the no of straps.
 
Calculation related to IR drop
 
 1. Average Current Through Each Strap=Istrapavg=(Itotal)/(2*Nstraps)mA
 
 2. Appropriate Ir Drop At The Center Of The Strap=Vdrop or IRdrop
                                                                                     =IstrapAvg*Rs*(W/2)*(1/Wstrap)  
                                                 
 3. Number Of Straps Between Two Power Pads
 
     Nstrappinspace=Dpadspacing/Lspace.
     MIN Ring Width = wring = Ip/Rj Microm

2. Ground bounce (power bounce):

When a lot of transistors are switching at the same time i.e., from 0 to 1, there may be a possibility that some charge may leak through it which leads ground voltage to jump to some active voltage( > Vil ).

3. EM violations:

Because of high current density, electron may move from one place to another place.

Overcomes:
For I-R drop:

-power routing should be done from top layer
-increase the number of power straps
-increase the width of the metal
-adding decaps
-using low power techniques

For EM violations:

-double width
-downsizing the cells
-metal slotting.