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PHYSICAL DESIGN: It is the process of transforming a circuit description into physical layout which describes the position of cells and routes for the interconnections between them.
The design flow deals with various steps involved such as follows:

Synthesis Netlist


Sanity checks



Clock Tree Synthesis (CTS)


Timing Closure

Physical Verification

Sign Off

Sanity checks has to be performed before every stage in order to check whether our design is meeting our design requirements for the next stage (or) whether it is properly designed.

Basically, a code(program) is developed that explains us the RTL characteristics of the chip to be designed. That should be done by front end engineers.
The developed code is compiled and as a result, a synthesis netlist is obtained. It contains the gate level model for the respective code.

.def is the output file at each step. After routing, the obtained .def file is fed to parasitic extraction tool like StarRC, QRC etc.., that contains its own extraction engine for the extracting R and C parasitics. As a result, .spef is generated.
It is further given as an input to STA engine(eg. Prime time) for timing analysis. If any setup and hold violations are obtained, we have to iterate from routing stage till setup and hold slacks met. 

The design compilers or tools used basically and mostly are
1. Synopsys.
2. Cadence
The other tools used are magma and mentor graphics.

The cost factors for physical design are area, power and timing.

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