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Clock Tree Synthesis
CLOCK TREE SYNTHESIS (CTS)

It is the process of creating the clock path from clock source to clock sinks.
The main goals of CTS is:
1. distributes clock to all sequential cells through entire design.
2. balances skew and minimizes insertion delay by proper buffering.
3. should meet timing and power requirement.
4. to meet design rule constraints(DRC) like max. trans., max. cap, max. fanout.
It begins at SDC_defined clock(clock source) and ends at sinks. Sinks are the pins of cells that receives clock.

Inputs for CTS are:
1. clockspec.tcl
-contains target skew.
-contains min. delay and max. delay.
-buffers/inverters for building clock tree.
-defined NDR(Non-Default Rules) like double spacing, double width etc..,
-contains CTS constraints/exceptions.
2. .def of placement.
(*H-tree is the mostly used algorithm for clock tree synthesis)

Clock nets are most sensitive and high fanout nets. So, NDR are applied after completion of placement stage in order to avoid crosstalk and electron migration problems that may arise in CTS stage i.e., after clock propagation.
Non-default rules are user-defined rules like double/triple width(avoids electron migration), double/triple spacing(crosstalk), shielding etc.., It hardens the clock

Clock signal is routed first when compared to that of signal nets(data) as those nets are high fanout nets and so, they require more routing resources. If the signal routing is before CTS, there may be the possibility of crosstalk and congestion as the req. routing resources become limited.

Buffers are added for balancing skew and minimizing the insertion delay.
In MPCTS/MSCTS(CTS algorithm), big buffers are to be added for increasing drive strength. These buffers are called as "Anchor buffers". They can drive >= 1000 microns.
MPCTS: Multi Point CTS
MSCTS: Multi Source CTS

Clock Tree optimization: done by
-buffer insertion
-gate sizing
-buffer relocation
-level adjustment
-HFN synthesis
-clock is to be shielded to avoid coupling of noise to other signals as clock is a high switching net(aggressor).
-Hold violation should be fixed first and then setup violations.

Different clock end points are:
stop pins: clock won't propagate after this pin.
exclude/ignore pins: not considered for clock propagation.
float pins: same as stop pin but internal clock latency of it is considered for clock tree.