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Placement
PLACEMENT

Placement is the process of automatically assigning correct position to standard cells on the chip with no overlapping.By global placement outside of standard cells will placed inside roughly.By the detailed placement the standard cells will place in site rows(legalize placement).In placement stage we check the congestion value by GRC map.
 
Placement
 
Basic Introduction
 
After you have done floorplanning, i.e. created the core area, placed the macros, and decided the power network structure of your design, it is time to let the tool to do standard cell placement. The tool determines the location of each of the components (in digital design, standard cell instantiations) on the die. Various factors come into play, like the timing requirement of the system, the interconnect lengths and hence the connections between cells, power dissipation etc. The interconnect lengths depend on the placement solution used, and it is very important in determining the performance of the system as the geometries shrink. Placement also determines the routability of your design.
Placement does not just place the standard cells available in the synthesized netlist. It also optimizes the design, thereby removing any timing violations created due to the relative placement on die.
 
Inputs To Placement Stage
 
Netlist
Mapped and Floorplannned Design
Logical and Physical Libraries
Design Constraints
 
 
Output of Placement Stage

 
Physical Layout Information
Cell placement location
Physical Layout, timing, and technology information of logical libraries
 
 
 
Below are key task perfomed during Placement stage

1. Special Cell Placement :- Placement of Well-Tap Cells, End-Cap Cells, Spare Cells, Decap Cells, JTAG and Other Cells Close to the I/Os
 
2. Optimizing and Reordering Scan Chains
 
3. Plaement Methodology :- Congestion Driven Placement Timing Driven Placement
 
4. Logic optimization In Placement
 
5. Major Placement Steps :- Virtual Placement, HFN synthesis, Initial (Global) Placement, Detailed, placement (Legalization) –Refine Placement
 
 
Post Placement Analysis-

1. Timing, Congestion Analysis
 
2. Placement Congestion: cell density
 
3. Global Route Congestion
 
Power Planning Basics
 
Power Planning is one of the most important stage in Physical design. Power network is being synthesized, It is used provide power to macros and standard cells within the given IR-Drop limit. Steady state IR Drop is caused by the resistance of the metal wires comprising the power distribution network. By reducing the voltage difference between local power and ground, steady-state IR Drop reduces both the speed and noise immunity of the local cells and macros.
Power planning management can be divided in two major category  first one is core cell power management and second one I/O cell power management. In  core cell power planning  power rings are formed around the core and macro.In IO cell power planning  power rings are formed for I/O cells and trunks are created between core power ring and power pads. 
In addition  trunks are also created for macros as per the power requirement.
power planning is part of  floor plan stage. In power plan, offset value for rings around the core and vertical and horizontal straps is being define
I/O cell library contains I/O cell and VDD/VSS pad cell libraries. It also contain IP libraries for reusable IP like RAM, ROM and other pre designed, standard, complex blocks.
 
Input Required In Power Planning

1. Database with valid floorplan 
2. power rings and power straps width
3. Spacing between VDD and VSS Straps
      
Output Of Power Planning

Design with Power Structure
 
Scan Chain

Scan chain is a technique used in design for testing. The objective is to make testing easier by providing a simple way to set and observe every flip-flop in an IC.The basic structure of scan include the following set of signals in order to control and observe the scan mechanism.
 
Scan_in and scan_out define the input and output of a scan chain. In a full scan mode usually each input drives only one chain and scan out observe one as well .
 
A scan enable pin is a special signal that is added to a design. When this signal is asserted, every flip-flop in the design is connected into a long shift register.
 
Clock signal which is used for controlling all the FFs in the chain during shift phase and the capture phase. An arbitrary pattern can be entered into the chain of flip-flops, and the state of every flip-flop can be read out.
 
Scan Chain Reordering
 
Scan chains are long shift registers for ATPG purposes. Since these chains are stitched pre-layout, these need not be layout friendly. Without re-ordering of chains, scan chains contribute to a long total wirelength. From a routability perspective it is important to reduce total wirelength. This reduces (limited) metal demand and acts to reduce congestion. Stray chains (unordered) may require repeaters and an increase in utilization. Although timing issues may not be expected since the chains are merely shift paths running at low atpg shift frequency, this might be an issue if chain quality is too poor.
 
Types of Cell

There are different types of cells used in order to meet the physical design requirements. I have tried to list the down some important cells which will come across frequently 
 
Well Tap Cells
               
These library cells connect the power and ground connections to the substrate and n-wells, respectively.By placing well taps at regular intervals throughout the design, the n-well potential is held constant for proper electrical functioning.The placer places the cells in accordance to the specified distances and automatically snaps them to legal positions (which are the core sites).
 
End Cap Cells
 
           These library cells do not have signal connectivity. They connect only to the power and ground rails once power rails are created in the design. They also ensure that gaps do not occur between the well and implant layers. This prevents DRC violations by satisfying well tie-off requirements for the core rows.
 
Each end of the core row, left and right, can have only one end cap cell specified. However, you
 
can specify a list of different end caps for inserting horizontal end cap lines, which terminate the
 
top and bottom boundaries of objects such as macros. A core row can be fragmented (contains gaps), since rows do not intersect objects such as power domains. For this, the tool places end cap cells on both ends of the unfragmented segment.
 
Decap cells
 
cells are temporary capacitors added in the design between power and ground rails to counter functional failures due to dynamic IR drop.Dynamic I.R. drop happens at the active edge of the clock at which a high percentage of Sequential and Digital elements switch.Due to this simultaneous switching a high current is drawn from the power grid for a small duration.If the power source is far away from a flop the chances are that this flop can go into a metastable state due to IR Drop.To overcome this decaps are added. At an active edge of clock when the current requirement is high , these decaps discharge and provide boost to the power grid. One caveat in usage of decaps is that these add to leakage current. De caps are placed as fillers. The closer they are to the flop’s sequential elements, the better it is.
 
 
Decap cells are typically poly gate transistors where source and drain are connected to the ground rail, and the gate is connected to the power rail. when there is an instantaneous switching activity the charge required moves from intrinsic and extrinsic local charge reservoirs as oppose to voltage sources. Extrinsic capacitances are decap cells placed in the design. Intrinsic capacitances are those present naturally in the circuit, such as the grid capacitance, the variable capacitance inside nearby logic, and the neighborhood loading capacitance exposed when the P or N channel are open.One drawback of decap cells is that they are very leaky, so the more decap cells the more leakage. Another drawback, which many designers ignore, is the interaction of the decap cells with the package RLC network. Since the die is essentially a capacitor with very small R and L, and the package is a hug RL network, the more decap cells placed the more chance of tuning the circuit into its resonance frequency. That would be trouble, since both VDD and GND will be oscillating. I have seen designs fail because of thisDesigners typically place decap cells near high activity clock buffers, but I recommend a decap optimization flow where tools study charge requirements at every moment in time and figure out how much decap to place at any node. This should be done while taking package models into account to ensure resonance frequency is not hit.

Spare cells
       
These are just that. They are extra cells placed in your layout in anticipation of a future ECO. When I say future, I mean after you taped out and got your silicon back. After silicon tests complete, it might become necessary to have some changes to the design. There might be a bug, or a very easy feature that will make the chip more valuable. This is where you try to use the existing “spare” cells in your design to incorporate the design change. For example, if you need a logic change that requires addition of an AND cell, you can use an existing spare AND to make this change. This way, you are ensuring that the base layer masks need no regeneration. The metal connections have changed, and hence only metal masks are regenerated for the next fabrication.
Kinds of spare cells: There are many variants of spare cells in the design. Designs are full of spare inverters, buffers, nand, nor and specially designed configurable spare cells.
Inserting Spare Cells
Spare cells need to added while the initial implementation. There are two ways to do this.
The designer adds separate modules with the required cells. You start your PnR with spare cells included, and must make sure that the tool hasn't optimized them away. There can be more than one such spare modules, and they will be typically named spare* or some such combination. The inputs are tied to power or ground nets, as floating gates shouldn't be allowed in the layout. The outputs are left unconnected.
Spare cells can also be added to design by including cells in Netlist itself.
 
 
Tie Cells

These are just that. They are extra cells placed in your layout in anticipation of a future ECO. When I say future, I mean after you taped out and got your silicon back. After silicon tests complete, it might become necessary to have some changes to the design. There might be a bug, or a very easy feature that will make the chip more valuable. This is where you try to use the existing “spare” cells in your design to incorporate the design change. For example, if you need a logic change that requires addition of an AND cell, you can use an existing spare AND to make this change. This way, you are ensuring that the base layer masks need no regeneration. The metal connections have changed, and hence only metal masks are regenerated for the next fabrication.
Kinds of spare cells: There are many variants of spare cells in the design. Designs are full of spare inverters, buffers, nand, nor and specially designed configurable spare cells.
 
Inserting Spare Cells
Spare cells need to added while the initial implementation. There are two ways to do this.
The designer adds separate modules with the required cells. You start your PnR with spare cells included, and must make sure that the tool hasn't optimized them away. There can be more than one such spare modules, and they will be typically named spare* or some such combination. The inputs are tied to power or ground nets, as floating gates shouldn't be allowed in the layout. The outputs are left unconnected.
Spare cells can also be added to design by including cells in Netlist itself.
 
Filler cells
 
Filler cells are used to establish the continuity of the N- well and the implant layers on the standard cell rows, some of the small cells also don’t have the bulk connection (substrate connection) because of their small size (thin cells). In those cases, the abutment of cells through inserting filler cells can connect those substrates of small cells to the power/ground nets. i.e. those thin cells can use the bulk connection of the other cells (this is one of the reason why you get standalone LVS check failed on some cells).

Special cells are required for implementing a Multi-Voltage design
 
Level Shifter

Level Shifter: Purpose of this cell is to shift the voltage from low to high as well as high to low. Generally buffer type and Latch type level shifters are available. In general H2L LS's are very simple whereas L2H LS's are little complex and are in general larger in size(double height) and have 2 power pins. There are some placement restrictions for L2H level shifter to handle noise levels in the design. Level shifters are typically used to convert signal levels and protect against sneak leakage paths. With great care, level shifters can be avoided in some cases, but this will become less practicable on a wider scale.
 
Isolation Cell
 
Enable Level Shifter

Retention Flops

Always ON cells

Power Gating Switches/MTCMOS switch.