CodeOne

FLOOR PLANNING

It is the first step of physical design flow that takes care of pin placement, macro placement etc.., using the area intelligently.
But before that, we should know about a concept called "Partitioning". 

Partitioning refers to the division of full chip into various parts, called as partitions (or) blocks (or) tiles in which each partition acts as a sub-chip. Each sub-chip contains macros, standard cells etc.., 

Macro is a memory/intellectual property.
All memories are macros but all macros are not memories. Ex. PLL etc..,
Types of Macros:
1. Memories
-RAM
-ROM
2. PLL/DLL
3. DAC/ADC
4. DSP cores
5. ARM cores
6. Graphic cores

The process of floorplanning is as follows:

 

Define core area and die area

⇓

Define i/p and o/p ports

⇓

Place macros

⇓

Hallos

⇓

Blockages

⇓

Power planning

Defining the die area and core area is carried out by the tool with reference to the synthesized netlist.